As the integrated circuit industry has explored ways of packing more circuits onto a given semiconductor substrate, more effort has been devoted to not only orienting the various devices in a planar fashion along the surface of the substrate, but also to orienting the devices vertically either by building the devices up from the substrate surface or by burying the devices in trenches formed within the face of the semiconductor body.
For example, a number of schemes for isolating customary planar devices with trench isolation regions are now known. Trench capacitors are also being employed on a commercial basis on the largest memory chips, such as 1-Mbit and 4-Mbit DRAMs.
Trench-like transistors have been employed in various forms. One of the earliest forms of a "trench-type" transistor uses various layers of semiconductive material to form a stack of a source/drain region covered by a layer that serves as a channel region and a top layer that serves as the other source/drain region. A groove or trench is cut through this stack. The groove or trench is coated or covered with a thin dielectric material which serves as the gate dielectric, and the remainder of the trench is filled with a conductive material plug which serves as a gate.
Other configurations employ a shallower trench-type structure or V-shaped groove where the trench or groove not only is coated or covered with a thin dielectric layer which serves as the gate dielectric, but which dielectric is further coated with a thin layer of conductive material to form the gate electrode; at least thin relative to the plug-type gate configurations. Also of interest in relationship to these types of structures are V-MOS devices with self-aligned multiple electrodes. Vertical CMOS transistors that are built up from the surface of the semiconductor wafer rather than buried into the substrate are also known, along with vertical FETs built into trenches where the gate is a thin layer inside the trench separated from another gate within the same trench by some sort of structure. Other proposed vertical FETs include a structure where a trench contains a cylindrical gate and one source/drain is positioned at the bottom of the trench with its contact running through the middle of the cylindrical gate. Also being investigated are trench-type structures which incorporate both transistors and capacitors into the trenches in some manner.
From the above brief history, it is noted that more complex devices are being designed for trench manufacture. As noted, the present challenge for trench technology involves placing more than one device in the same trench, such as a transistor and other element to form a dynamic or static random access memory (DRAM or SRAM) memory cell.
Nevertheless, as trench technology is still developing, a need exists for additional trench structures, particularly of the newer, multiple device type, so that the best alternatives may be made available and considered in the fabrication of extremely high density integrated circuits. Very few of the proposed trench structures have actually been implemented in commercial integrated circuit chips. There is a need for future SRAM cells employing the new trench technologies, particularly those which provide a low soft error rate (SER).